SCHEMATIC DESIGN ENGINEER

Job Description: - Design, optimize, and verify SRAM schematic libraries for high-speed, low-power, and automotive products across various process technology nodes ranging from 90nm to 2nm. - Participate in and optimize design and Quality Assurance (QA) flows/processes. - Collaborate with Layout Engineers to review and optimize schematics. - Perform characterization including delay, setup/hold, power, NLDM, CCS, AOCV, and LVF models. - Perform power, performance, and area (PPA) benchmarking, comparison, and evaluation. - Integrate and test memory on silicon testchips, and provide silicon post-silicon/evaluation reports.

Job Requirements: - Passion for the semiconductor industry and a strong capacity for learning. - Solid fundamental knowledge of mosfet, basic logic gates, flip-flops, etc. - Understanding of delay, setup/hold time, fan-in, fan-out, RC modeling, power, etc. - Prior experience in design simulation is a plus. - Programming skills in at least one language: C, Perl, TCL, Python, or Shell scripting. - Hands-on experience with the Linux environment is an advantage. - Preference given to candidates proficient in Verilog/VHDL and Testbench writing. - Familiarity with EDA tools from Synopsys, Cadence, or Mentor (Siemens EDA) is a plus.

Benefit: · Competitive Compensation: Attractive salary (negotiable based on experience), 13th-month salary, plus performance, quarterly, project, and holiday/Tet bonuses. · Career Growth: Hands-on experience with cutting-edge technologies across diverse, large-scale projects. · Culture & Work-Life Balance: Youthful, dynamic, and creative environment with a 5-day work week (Monday–Friday). · Comprehensive Benefits: Full statutory insurance (SI, HI, UI), annual health check-ups, company trips, team building, sports clubs, and company events.