STANDARD CELL DESIGN ENGINEER

Job Description: - Design and optimize standard cell libraries (combinational & sequential cells) - Perform schematic design and layout verification (DRC/LVS) - Characterize standard cells across PVT corners - Generate and validate Liberty (.lib) files for timing and power - Collaborate with physical design and front-end teams - Optimize PPA (Power, Performance, Area)

Requirements: - 3+ years of experience in IC design / standard cell development - Strong understanding of CMOS digital design fundamentals - Strong Hands-on experience with SPICE sim - Experience with Liberty characterization and timing analysis - Understanding of PVT corners, timing arcs, setup/hold analysis Fluent English communication is REQUIRED: - Able to participate actively in technical discussions and meetings - Comfortable explaining design concepts and issues in English - Able to read/write technical documents and communicate with global team daily Advanced Node Expertise (Required): - Hands-on or strong experience with advanced nodes (≤7nm, FinFET) - Solid understanding of 2nm-class technologies (GAA / nanosheet transistors) - Awareness of challenges in advanced nodes: - Variability, leakage, parasitics, IR drop, EM, signal integrity - Layout-dependent effects (LDE) - Experience working with foundry PDKs Preferred: - Knowledge of low-power techniques (multi-Vt, multi-Vdd) - Scripting (Python, Tcl) - Experience working with foundry PDKs

Benefit: - Competitive Compensation: Attractive salary (negotiable based on experience), 13th-month salary, plus performance, quarterly, project, and holiday/Tet bonuses. - Career Growth: Hands-on experience with cutting-edge technologies across diverse, large-scale projects. - Culture & Work-Life Balance: Youthful, dynamic, and creative environment with a 5-day work week (Monday–Friday). - Comprehensive Benefits: Full statutory insurance (SI, HI, UI), annual health check-ups, company trips, team building, sports clubs, and company events.