STANDARD CELL LAYOUT ENGINEER

Job Description: - Layout design for basic logic gates: AND, OR, XOR, etc. - Layout design for flip-flop families (DFF) and Standard Cells. - Perform DRC (Design Rule Checking) and LVS (Layout Versus Schematic) checks. - Perform Quality Assurance (QA) verification.

Job Requirements: - Passion for working in the semiconductor/IC design industry. - Solid basic knowledge of logic gates and flip-flops. - Hands-on experience with the Linux environment is an advantage. - Ability to read and understand English technical documentation; good written and spoken English is a plus.

Benefit: - Competitive Compensation: Attractive salary (negotiable based on experience), 13th-month salary, plus performance, quarterly, project, and holiday/Tet bonuses. - Career Growth: Hands-on experience with cutting-edge technologies across diverse, large-scale projects. - Culture & Work-Life Balance: Youthful, dynamic, and creative environment with a 5-day work week (Monday–Friday). - Comprehensive Benefits: Full statutory insurance (SI, HI, UI), annual health check-ups, company trips, team building, sports clubs, and company events.