LAYOUT DESIGN ENGINEER

- Perform cell and chip-level schematic entry, IC layout, and verification (LVS, DRC, ERC). - Chip floorplanning and I/O ESD routing, and support/assist in tapeout and documentation. - Collaborate with design engineers to prepare IC layouts for tapeout on technologies such as CMOS, SOI, SiGe, and BICMOS. - Use revision control systems for design database management. - Create documentation. - PDK modification and SKILL scripting for design and CAD teams to support layout flows is a plus.

- BS Degree in electrical engineering, computer science, or equivalent. - Knowledge and understanding of semiconductor technology and layout verification (Design Rule Check, Layout vs. Schematic). - Solid understanding of layout implementation flow and IC Design Methodologies using Cadence Virtuoso. - Unwavering commitment to quality work and supporting R&D efforts. - Relevant experience and a willingness to learn is necessary. - Experience with EDA tools such as Cadence Virtuoso, Assura, PVS, and Calibre. - Experience with Linux and Windows computer systems. - Proficiency in Linux shell scripts, SKILL, AMPLE, Perl, and Python is a plus. - Proven capability to work both independently and on a team. - Excellent interpersonal and communication skills. - High self-motivation with effective communication and good troubleshooting and debugging skills.

We are Qorvo. We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure markets – we are a place to innovate and shape the future of wireless communications. It starts with our employees. As a unified global team, we bring a commitment to excellence, growth and a passion for creating what's next. Explore the possibilities with us. We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability.