DFT Engineer (Mid/Senior)

## Build the Test Infrastructure Behind Automotive ICs

Joining the DFT team, you will have a chance to work with the highest standard of DFT quality for functional-safety and low DPPM requirements. As a DFT Engineer at BOS, you will help turn complex designs into production-ready silicon. You will work across the DFT flow, from architecture and DFT insertion through ATPG, verification, DFT timing closure, and silicon bring-up support. This is an opportunity to contribute to advanced DFT features across automotive SoCs and Physical AI products while collaborating closely with RTL, verification, physical implementation, IP, and test engineering teams.

## What You Will Do

* Design, implement, and verify block-level and top-level DFT logic, including scan compression, MBIST, BISR, boundary scan, and LBIST, and in-system test.

* Develop DFT SDC constraints and analyze timing for scan, MBIST, and IJTAG modes. Resolve DFT clock architecture, timing, power, and physical-design issues with physical implementation (STA) teams.

* Contribute to advanced DFT features, including LBIST, PCIe, UCIe chiplet test, memory repair, hierarchical DFT and SSN (Streaming Scan Network), according to product needs.

* Debug RTL-level testability issues, drive coverage improvement to meet automotive requirement, and solve DFT simulation issues.

* Partner with RTL, verification, IP, physical implementation, and test engineering teams to balance test quality, test time, and implementation constraints.

## What You Bring

* Bachelor’s degree or higher in Electronics Engineering, Computer Engineering, Computer Science, or a related field.

* From 2 to 7 years of hands-on experience in ASIC DFT implementation.

* Solid understanding of scan insertion and compression, ATPG stuck-at and transition fault models, coverage analysis, and DFT simulation.

* Experience using industry-standard DFT design and implementation tools from Siemens and Synopsys.

* Ability to debug technical issues independently, communicate clearly in English, and work effectively with cross-functional teams.

## Nice to Have

* Experience in one or more advanced DFT areas: DFT SDC and STA, BISR/BIRA, LBIST, boundary scan, Tessent SSN or post-silicon debug.

* Experience with full-chip DFT sign-off, automotive SoC development, functional safety, or ISO 26262-oriented design practices.

* Experience delivering ATE patterns, supporting silicon bring-up, or improving test coverage and test time for chip production.

* For senior candidates: experience with full-chip DFT implementation, sign-off, tape-out, silicon diagnosis, or integration of PHY hard-macro and ETM models.

Why join us?

• Competitive salary + 13th month bonus
• Retention bonus
• Meals provided (Breakfast, Lunch, Dinner), Private Health Insurance, Hybrid work model
• We care about your well-being and personal growth with Fun English classes, Happy Beer Parties, Football & Badminton Club, and more!
• Be part of a cutting-edge R&D center focused on automotive SoCs