Senior Physical Implementation Engineer (STA)

Pre-Layout Support & Constraint Development

• Assist in creating and maintaining SDC constraints under supervision
• Support physical-aware synthesis using Design Compiler / Fusion Compiler
• Help prepare scan stitching–ready netlists and test-mode timing constraints
• Assist with UPF-based low-power intent modeling, including isolation and level shifter handling
• Generate basic pre-layout timing reports and review results with senior engineers

Post-Layout STA & Timing Analysis

• Run post-layout STA using PrimeTime for assigned blocks or modes
• Analyze setup and hold timing violations and support debug activities
• Assist in timing ECO execution and validation
• Support timing correlation between pre-layout and post-layout stages
• Learn MCMM concepts, derating, and physical-effect-aware timing analysis

Learning & Engineering Development

• Work closely with senior engineers to learn Bos Semiconductors’ STA and implementation methodologies
• Participate in timing reviews and sign-off discussions
• Follow established flows, scripts, and quality checklists
• Continuously improve understanding of STA theory, Synopsys tools, and low-power design

• B.S. in Electrical Engineering or related field
• At least 3 years of experience, including internships or academic projects
• Basic understanding of digital design and STA fundamentals
• Familiarity with Linux environments and EDA workflows
• Prefers:
  • Exposure to Synopsys PrimeTime, Design Compiler, or Fusion Compiler
  • Basic knowledge of SDC and UPF
  • Strong willingness to learn and grow in a physical implementation role

• Competitive salary + 13th month bonus
• Retention bonus
• Lunch provided, Private Health Insurance, Hybrid work model
• We care about your well-being and personal growth with Fun English classes, Happy Beer Parties, Football & Badminton Club, and more!
• Be part of a cutting-edge R&D center focused on automotive SoCs