PACKAGING ENGINEER

• Define package type, pinout, and mechanical specs for Fvision SoC (BGA, QFN, LGA, or SiP) based on PPA and application needs. 
• Manage OSAT partner selection, RFQ, and qualification: assembly qualification, JEDEC JESD22 reliability testing, production approval. 
• Perform or review package thermal analysis (θJB, θJC) and collaborate with PD on die power maps and bump placement. 
• Lead package SI/PI analysis: die-package co-simulation, PDN modeling, and ESD/latch-up evaluation. 
• Define FAI and IQC criteria for packaged samples from OSAT; maintain qualification documents and audit records. 

• Bachelor’s or Master’s in Electronic Engineering, Materials Engineering, or related field. 
• 5+ years semiconductor packaging or OSAT management experience. 
• Solid knowledge of package types (BGA, QFN, LGA, flip-chip, WLCSP) and assembly processes. 
• Experience with JEDEC reliability qualification standards (JESD22 family). 
• Familiarity with thermal simulation (ANSYS Icepak, Flotherm) or package SI/PI tools. 
• Good English and Vietnamese communication skills. 

Nice to Have 

• Advanced packaging 
• Automotive or aerospace packaging qualification (AEC-Q100 / DO-160). 

Successful candidates will be part of a friendly, motivated and committed talent teams with various benefits and attractive offers:

• Competitive compensation package, aligned with capabilities and performance.
• 100% salary during the probation period.
• Comprehensive benefits and welfare package (FPT Care, annual company trips, team building activities, annual health check-ups) in line with a large-scale corporation.
• Opportunities to expand your professional network with leading semiconductor partners.
• Exposure to a diverse ecosystem across the semiconductor value chain, including PMIC, IP Solutions, Engineering Services, ATE & Packaging, Camera & Drone, and IoT Devices.
• Access to professional training and development programs within FPT Corporation.
• Working hours: 9:00 AM – 6:00 PM, Monday to Friday.