RTL Design Engineer (Experienced)

• Perform IP/subsystem/SoC RTL design and integration using Verilog/SystemVerilog.
• Contribute to RTL design and integration in one of the following areas: SoC/Chip Top, DDRAM, System BUS/NoC, or NPU/VPU/TPU accelerators, based on your technical background.
• Integrate and develop key SoC components such as CPU/NPU, DDR, NoC/interconnect, peripheral IPs, and accelerator datapaths.
• Analyze and optimize system performance, memory access, bandwidth, latency, and dataflow where applicable.
• Perform SDC, Lint, CDC, and RDC checks and debug RTL/system-level integration issues.

• Bachelor’s, Master’s, or Ph.D. in Electrical/Computer Engineering or related field.
• 3+ years of experience in ASIC/SoC RTL design or integration.
• Strong experience with Verilog/SystemVerilog and good understanding of SoC design flow and methodology.
• Hands-on experience with SDC, Lint, CDC, RDC, and RTL/system-level debugging.
• Hands-on experience or relevant technical knowledge in at least one of the following tech stacks:

SoC Top / Chip Top Integration

• Experience with SoC/Chip Top integration, including CPU, NPU, DDR, NoC, and high-speed peripheral IPs.
• Strong knowledge of clock/reset, interrupt, address map, power-domain, and system-level integration.
• Good understanding of AMBA AXI/AHB/APB and strong SoC-level debugging capability.

DDRAM Integration

• Experience with DDR4/DDR5 or LPDDR4/LPDDR5/LPDDR5X.
• Experience integrating DDR Controller and DDR PHY, including DFI and AXI interfaces.
• Good understanding of DDR initialization, training, refresh, read/write datapath, and timing.
• Knowledge of controller architecture, scheduling, arbitration, bank/rank management, and QoS.

System BUS / NoC Integration & Implementation

• Experience with SoC interconnect or NoC RTL design/integration.
• Strong knowledge of AMBA CHI/AXI/AHB/APB, including transaction handling, ordering, arbitration, and QoS.
• Experience with BUS/NoC performance analysis and optimization, including bandwidth, latency, throughput, congestion, and bottleneck analysis.

NPU / VPU / TPU Integration

• Experience with NPU, VPU, TPU, or other AI/ML accelerator RTL design or integration.
• Good understanding of AI compute architectures such as MAC/PE arrays, systolic arrays, convolution engines, GEMM/GEMV, and tensor datapaths.
• Knowledge of AI inference dataflow, local SRAM, DMA, buffering, memory bandwidth, and datapath/pipeline optimization.

We welcome candidates who have relevant hands-on experience or strong technical knowledge in one or more of these areas, even if they have not owned the entire scope before.

Why join us?

• Competitive salary + 13th month bonus
• Retention bonus
• Meals provided (Breakfast, Lunch, Dinner), Private Health Insurance, Hybrid work model
• We care about your well-being and personal growth with Fun English classes, Happy Beer Parties, Football & Badminton Club, and more!
• Be part of a cutting-edge R&D center focused on automotive SoCs.