SoC Design Verification Engineer (Experienced)

Role Overview

We are looking for experienced SoC Design Verification Engineers to join our team and contribute to complex SoC verification.

Depending on your experience and technical background, you will focus on one of the following areas: BUS & Performance, DRAM, SoC Testbench & Emulation, DFT/GLS, CoreSight & Debugger, NPU, OCA (Open Chiplet Atlas).

Responsibilities

• Perform IP/subsystem/SoC-level functional verification using SystemVerilog/UVM.
• Develop verification plans and test plans based on design specifications and architecture requirements.
• Perform verification across multiple aspects of the design, including functional verification, SDC/CDC verification, and gate-level simulation (GLS).

Requirements            

• Bachelor’s, Master’s, or Ph.D. in Electrical/Computer Engineering or related field.
• 2+ years of experience in SoC/IP Design Verification; 3+ years preferred for senior/ownership roles.
• Proficient in SystemVerilog, UVM, C/C++, and Python.
• Strong debugging, problem-solving, and teamwork skills.
• Solid understanding of SoC design flow and verification methodology.
• Hands-on experience or relevant technical knowledge in at least one of the following tech stacks:

· BUS & Performance: Understand SoC bus / interconnect, experience with AMBA protocols (AXI/AHB/APB), bandwidth and latency analysis. Good debugging and problem-solving skills using simulation and waveform analysis.

· DRAM: Understand DRAM architecture, DDR/LPDDR, memory subsystem or memory controller verification.

· SoC TB & Emulation: Set up, bring up, and maintain SoC-level testbench and emulation environments; debug SoC boot flows and HW/SW integration issues; and develop Python-based automation for environment setup, regression, and verification workflows.

· DFT / GLS: Setting up, bringing up gate-level simulation, debugging GLS, X-propagation, understanding of DFT architecture and flows, including MBIST, LBIST, POST, and IST.

· CoreSight & Debugger: Hands-on experience with Arm CoreSight, JTAG, CPU debug, trace infrastructure, and system-level debug; experience with SoC-level testbenches and CPU-based verification.  

· NPU / AI Accelerator:Strong understanding of NPU/AI accelerator architecture and compute/data flow; hands-on experience porting Python-based testbenches, binary test vectors, and reference models to SystemVerilog/UVM-based verification environments; knowledge of NPU performance verification, including throughput, latency, bandwidth, and memory traffic analysis.

· Chiplet / OCA: Understand chiplet architecture and die-to-die communication; experience with chiplet/subsystem integration and verification; knowledge of UCIe/I3C and interconnect protocols such as AXI/CHI/PCIe/CXL; exposure to SoC-level testbenches or multi-chiplet/co-simulation environments.

We welcome candidates who have relevant knowledge or hands-on exposure to one or more of these areas, even if they have not owned the full scope before.

Why join us?

• Competitive salary + 13th month bonus
• Retention bonus
• Meals provided (Breakfast, Lunch, Dinner), Private Health Insurance, Hybrid work model
• We care about your well-being and personal growth with Fun English classes, Happy Beer Parties, Football & Badminton Club, and more!
• Be part of a cutting-edge R&D center focused on automotive SoCs.