SENIOR STAFF EGINEER DIGITAL VERIFICATION

In your new role you will: - Be responsible for developing SystemVerilog – UVM testbench and solve potentially complex problems related to test bench development - Debug failing test cases to root cause - Be responsible for defining and writing a functional coverage model - Participate in reviews to ensure test bench meets quality and is complete - Contribute to verification perspective in Design and Concept meetings - Ensure test bench meets sign-off targets, including coverage, functional safety and test bench qualification - Develop deep understanding of complex IPs/SoCs and take end-to-end ownership of their verification - Independently identify sub-modules that are particularly suitable for Formal Verification and apply this methodology - Proactively help increase efficiency of verification activities and mitigate risks early - Contribute to enhancing Verification strategy and architecture of IP/SoC testbenches

You are best equipped for this task if you have: - A degree in Electrical/Electronic Engineering, Computer Science or equivalent - More than 8 years of experience within the semiconductor industry - Proven experience of ownership of IP/SoC verification including delivering to metric targets - Ability to understand complex design specification, derive features and test bench architectures from concept - Capability to use industry-standard EDA tools - Good time management skills and the ability to deliver to high-quality requirements under pressure - Safety-first approach with ability to pay close attention to detail - Good programming skills, e.g. in C++, Python or Perl, as well as good Linux skills - Knowledge on functional safety ISO26262 is a plus. - Ability to clearly report issues and progress and communicate in English