SENIOR/STAFF CIRCUIT DESIGN ENGINEER

What You'll Be Doing - Design and develop CMOS special memory circuits including TCAM, BCAM, and multi-port SRAM for advanced process nodes - Own architecture definition and circuit implementation for ultra-high speed, ultra-low power, or high-density memory portfolios - Drive schematic entry, circuit simulation, layout planning, and design verification from bitcell to full array - Collaborate with CAD and frontend engineers to integrate designs into memory compiler flows and generate EDA models - Develop and verify bitcells, supervise physical layout design, and debug parasitic extraction results to meet performance targets - Support silicon bring-up and failure analysis, translating test data into design improvements for future releases The Impact You Will Have - Your memory designs will enable faster, lower-power chips across automotive, mobile, AI, and high-performance computing markets - The bitcells and architectures you develop will define performance benchmarks for Synopsys Foundation IP across multiple process nodes - Your debugging and failure analysis will improve yield and robustness, reducing costly respins and accelerating customer adoption - Collaboration with compiler teams will streamline design automation, reducing turnaround time for custom memory configurations - Mentorship you provide will build circuit design capability within the team, raising the technical bar for future releases

What You'll Need - Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or a related technical field - 3+ years of hands-on experience designing embedded CMOS memory circuits at 28nm or more advanced technology nodes - Proven experience with embedded memory design flow: architecture, circuit design, layout implementation, compiler integration, and timing model generation - Strong proficiency in bitcell design, circuit simulation tools like HSPICE or Spectre, and layout parasitic extraction - Deep understanding of SRAM, TCAM, BCAM, or multi-port memory architectures, with experience in failure analysis and memory test methodology - Experience with layout verification tools such as Calibre or ICV, and ability to debug DRC, LVS, and ERC issues; experience with TCAM or multi-port SRAM is a strong plus Who You Are - You can explain a complex circuit tradeoff to a product manager in two sentences without losing the technical nuance - When a simulation result does not match your intuition, you dig until you understand why, whether it is a model issue or a real design flaw - You are comfortable leading design reviews where you defend your architecture choices and incorporate feedback without losing momentum - Debugging energizes you; you treat a silicon failure as a puzzle to solve, not a setback - You balance detail orientation with pragmatism, knowing when to push for another optimization round and when to lock the design

The Team You'll Be Part Of => You will join the Foundation IP team in Ho Chi Minh City, a group focused on developing memory compilers and special memory solutions for advanced process nodes. The team works closely with CAD, frontend, and characterization engineers to deliver high-performance, low-power memory IP that ships in customer designs worldwide. Rewards and Benefits => We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.