Design Verification Intern
As a Design Verification Intern, you will help verify IP designs before tape-out, learning modern verification methodology on real silicon-bound projects. Your responsibilities will include:
- Read and understand design specifications, and help create test plans and coverage plans.
- Study the existing coverage group definitions and test cases, then write new tests, including constrained-random tests, to improve coverage.
- Run simulations, understand how the block under test operates, and debug failures.
- Work toward coverage improvement and closure.
- Contribute to improvements in the DV strategy, flow, and scripts.
- Collaborate with design engineers to resolve issues, and document your verification results.
What We're Looking For
- Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Electrical & Computer Engineering (expected to graduate in 2027 or 2028)
- Familiar with Verilog and SystemVerilog.
- Good English.
- Strong debugging and problem-solving skills, and the ability to work well in a team.
Nice to Have
- Knowledge of UVM.
- Experience with scripting languages such as Python or Perl, and a Linux working environment.
- Understanding of digital design fundamentals and mixed-signal design concepts.
Additional Compensation And Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
