IC Layout Engineer – Junior & Senior (1–4+ Years Experience)

Design and develop SRAM/ROM arrays and analog layouts, including PLL, ADC, LDO, and BGR circuits.

Apply advanced layout matching techniques and ensure DRC/LVS-clean layouts.

Experience with FinFET technology is an advantage.

Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field.

Good English communication skills, both written and verbal.

13th-month salary and project-based bonuses.

Annual salary reviews.

Premium health insurance coverage for you and your family.

Meal and phone allowances.

Training, mentorship, and opportunities to work on projects for global semiconductor clients across the US, Japan, South Korea, and Taiwan.

Team-building activities and an annual Year-End Party.