Physical Design Intern
As a member of the Marvell CCDS physical design team, you will take part in next-generation physical design implementation and verification of complex SoC designs. Your responsibilities will include:
- Block-level layout implementation and timing closure.
- Static timing analysis (STA), crosstalk analysis, and timing closure.
- Synthesis and physical synthesis.
- Power, IR drop, and electromigration (EM) analysis.
- Physical verification (LVS, DRC, ERC).
- Engineering change order (ECO) implementation.
What We're Looking For
- Currently enrolled in a Bachelor's degree program in Electrical Engineering, Computer Engineering, or a related field (expected to graduate in 2027)
- Experience with scripting or programming in Tcl/Tk or Perl.
- Detail-oriented and self-motivated, with the ability to work well in a team.
- Good verbal and written communication skills in English.
Nice to Have
- Previous physical design and automatic place-and-route experience with Synopsys, Magma, or Cadence P&R tools.
- Previous synthesis or static timing analysis experience.
Additional Compensation And Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
