Senior Physical Design Engineer – IC Design (3+ Years Experience)

Execute block-level and full-chip Place & Route, including floorplanning, Clock Tree Synthesis (CTS), timing closure, and physical verification.

Proficiency in Cadence Innovus or Synopsys ICC2, with strong Tcl scripting skills.

Experience with Python or Perl is an advantage.

Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field.

Good English communication skills, both written and verbal.

13th-month salary and project-based bonuses.

Annual salary reviews.

Premium health insurance coverage for you and your family.

Meal and phone allowances.

Training, mentorship, and opportunities to work on projects for global semiconductor clients across the US, Japan, South Korea, and Taiwan.

Team-building activities and an annual Year-End Party.